Founding Engineer – FPGA, RTL, & ASIC Architect at Zettascale

At Zeta, we are building the next NVIDIA to accelerate AI discovery. Our XPU chips are state-of-the-art AI compute enginesVersatile and efficient enough to support Agitationand finally Archaeological Survey of IndiaWithout the need for large-scale power infrastructure.

The team includes exceptional engineers obsessed As we push the boundaries of what’s possible in computing, And now we are looking for our next technical member!

you are

  • Willing to make every possible effort and do your life’s work
  • Willingness to be radical while pushing technical limits
  • A tech powerhouse that loves to work across the hardware-software boundary
  • deep passionate And obsessed with computing and AI
  • The hunger to create something that really matters

Your background (important in bold)

  • Background in Electrical Engineering, Computer Engineering, or equivalent field
  • Strong Digital Design Fundamentals (VLSI, RTL, pipelining, clocking/reset strategies, latency/throughput tradeoffs, clean microarchitecture)
  • RTL Quality Discipline (Lint, CDC/RDC, X-Prop Awareness, Assertion/SVA, Code Review Sanitation)
  • Synthesis/Constraint Expertise (Time closing with SDC constraints, synthesis/PPA iteration, physical design)
  • Proficiency with front-end toolchains (VCS/Xcellium/Questa, Verilator, Spyglass-style linting, DC/Genus-class synthesis)
  • Manufacturing/Flow Automation and Tooling (Python, Tcl, Nix)
  • Work on architecture, verification, and physical design To achieve PPA targets (Area/Power/Complete)
  • Experience designing compute datapaths and memory subsystems For AI accelerators, GPUs, or high-performance CPUs (bandwidth/latency-driven design)

huge plus if

  • High-speed interface/IP integration experience (PCIe, CXL, DDR/HBM, Ethernet, SERDES)
  • DFT-aware RTL (Scan-friendly coding patterns, test hooks, clean resets, well-defined clock gating strategy)
  • Experience writing/keeping reusable IPs (Parameterization, clean bus protocol, well-structured interfaces)
  • 1+ years (or equivalent) in designing synthetic RTL. (SystemVerilog/Verilog) for ASICs and/or high-performance FPGA prototyping
  • HW/SW limit experience (fetching drivers/firmware, performance counters, profiling, build system)
  • Experience in systems programming (Linux kernel module, low-level)
  • Autodidactic polymath with a strong mathematical background
  • Someone who doesn’t panic when faced with nearly impossible technical challenges

opportunity

  • Be one of the first employees to shape revolutionary technology
  • Work directly with the founding team of exceptional engineers in our San Francisco headquarters
  • Own important decisions that will affect the future of AI computing
  • Develop into a technology leader as we grow
  • Highly competitive compensation + significant equity

This is your chance to do your life’s work. A chance to create something that will be remembered. To be fanatical about a technological moon that will actually matter more than 100 to 1,000 years from now.



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