Second IC :) – Sam Zeloof

Homemade 1000+ Transistor Array Chip

In 2018 I created the first lithographically fabricated integrated circuit in my garage fab. I was a senior in high school when I built the Z1 amplifier, and I’m now a senior in college so there have been some long overdue improvements to the hobbyist silicon process.

The Z1 had 6 transistors and was a great test chip for all the processes and devices being developed. The Z2 has 100 transistors on a 10μm polysilicon gate process – the same technology as Intel’s first processors. My chip process is a simple 10×10 array of transistors for testing, characterizing and tweaking but it is a big step closer to more advanced DIY computer chips. The Intel 4004 has 2,200 transistors and I have now created 1,200 transistors on the same piece of silicon.

Earlier, I used to make chips using metal gate process. The aluminum gate has a large work function gap with the silicon channel beneath it resulting in a high threshold voltage (>10V). I used these metal gate transistors in some fun projects like guitar distortion pedal and a Ring Oscillator LED Blinker But both of them require one or two 9V batteries to run the circuit due to the high Vth. By switching to a polysilicon gate process, I get a ton of performance benefits (self-aligned gate means less overlap capacitance) including a much lower Vth that makes these chips compatible with 2.5V and 3.3V logic levels. The new FET has excellent characteristics:

NMOS Electrical Properties:
Vth             = 1.1 V
Vgs MAX         = 8 V
Cgs             = <0.9 pF
Rise/fall time  = <10 ns
On/off ratio    = 4.3e6
Leakage current = 932 pA (Vds=2.5V)

I was particularly surprised by the super low leakage current. This value increases approximately 100 times in ambient room light.

We now know that it is possible to make really good transistors with unclean chemicals, clean rooms, and household appliances. Of course, yield and process repeatability are reduced. I will do more testing to collect data on the statistics and variability of the FET properties but it looks good!

The chip is small, about a quarter of the die area of ​​my previous IC (2.4mm^2), making it hard to test. There is a simple 10×10 array of N-channel FETs on each chip that will give me a lot of characterization data. Since it’s such a simple design, I was able to create it using Photoshop. Columns of 10 transistors share a common gate connection and each row is connected together in series with adjacent transistors sharing a source/drain terminal. This is similar to NAND flash but I only did this to keep the metal pads large enough so I could probe them properly, if each FET had 3 pads to itself they would be too small.

It’s hard to express the excitement of seeing a nice FET curve displayed on a curve tracer after dipping a piece of rock in chemicals all day.

A single 10μm NMOS transistor can be seen below, with a slight misalignment in the metal layer (part of the left contact is open). Red outline is polycrystalline silicon, blue is source/drain.

So far I have made an opamp (Z1) and a memory-like array (Z2). More interesting circuits are certainly possible even with this low transistor density. The process required some tweaking, but now that I am able to consistently make good quality transistors I should be able to design more complex digital and analog circuits. It’s very hard to test each chip so I’m trying to automate the process and then post more data. I’ve built 15 chips (1,500 transistors) and know that at least one is a fully functional chip and at least two are “mostly functional”, meaning ~80% of the transistors work instead of 100%. There is no proper yield data yet. The most common fault is a drain or source that is smaller than the bulk silicon channel, not a leaky or short gate like my Z1 process.

I said earlier that the gate used to be made of aluminum and now it is silicon which makes the chips work much better. Silicon comes in the three varieties we care about: amorphous, polycrystalline, and monocrystalline. From left to right, these become more electrically conductive but they also become more difficult to deposit. In fact, monocrystalline Si cannot be deposited, you can only grow it as a seed (epitaxy) in contact with another mono-Si layer. Since the gate must be deposited over an insulating dielectric, poly is the best we can do. We can heavily dope polysilicon to make it more conductive.

A typical self-aligned polysilicon gate process requires toluene, a toxic and explosive gas, to deposit polycrystalline silicon layers. This may also be possible by sputtering or evaporating amorphous silicon and annealing it with a laser. A major theme of this DIY silicone process is to avoid expensive, difficult, or dangerous steps. So, I came up with a modified process flow. This is a variation on standard self-aligned methods to allow doping via high temperature diffusion rather than ion implantation. The effect of this is that I am able to buy a silicon wafer with polysilicon already deposited from the factory and pattern it to make transistors, rather than having to insert my own polysilicon in the middle of the process. This is a good short-term solution, but it would be best to design the polysilicon deposition process using the laser anneal method mentioned above.

Wafers are available with all kinds of materials already deposited, so I just had to find one with thick polysilicon (300 nm) with a thin layer of SiO2 (gate oxide, ~10 nm). I need a lot of 25 200mm (EPI, Prime, [1-0-0]P-type) wafers on eBay for $45 which is essentially a lifetime supply, so email me if you want one. Gate oxide is the most delicate layer and requires the most care during fabrication. Since I had already purchased a wafer with good high quality oxide, covered with a thick polysilicon layer and kept clean, I was able to eliminate all the aggressive cleaning chemicals (sulfuric acid, etc.) from the process and still make great transistors. Minimum process chemicals and equipment are listed below.

Chemicals used in home poly-gate process:
-Water
-Alcohol
-Acetone
-Phosphoric acid
-Photoresist
-Developer (2% KOH)
-N type dopant (filmtronics P509)
-HF (1%) or CF4/CHF3 RIE
-HNO3 for poly etch or SF6 RIE

Equipment used in home poly-gate process:
-Hotplate
-Tube furnace
-Lithography apparatus
-Microscope
-Vacuum chamber to deposit metal

Z2 “Get First” process (similar to standard self-aligning process but without field oxide):

I broke one of the test chips in half (functional Z2 but poor layer alignment and thin metal, about 300nm) and put it into my SEM for cross section:

Find the dust particle in the red circle below, use it to orient in the cross section views to come.

Because I’ve already purchased a wafer with gate oxide and polysilicon, I can’t grow field oxide. These thick oxide layers are typically used to hide dopants and require a long high temperature step that will oxidize all of my poly and leave none remaining. Therefore, my modified process uses an additional masking step (the “gate” mask is not typically found in the self-aligned process) which allows me to use the polysilicon as the dopant mask and the hard-baked photoresist as the field dielectric. This alternative processing results in the stepped structure that you can see in the orange area on the NMOS cross section above. The subtleties of this process are mentioned here, Read this Twitter thread,

This process is not ideal and I would like to make some changes so that it is CMOS compatible but it simplifies the build and makes it possible with a minimal set of tools. The 1µm dielectric layer (orange) would ideally be CVD SiO2 (it’s possible to make a TEOS oxide reactor at home) but I used a photoresist instead. Most photoresists can be baked around 250 °C to form a hard permanent dielectric layer that is an easy alternative to CVD or PECVD oxides. Spin-on-glass/sol-gel can also be used here. SiO2 etching is done with a buffered HF solution made from rust stain remover or RIE.

Image of giant mixed stitched die:

Thanks for following my work and feel free to contact me with your ideas!