Last month, Malaysian Prime Minister Anwar Ibrahim revealed in a post on Facebook that Intel was expanding its Malaysian chip-making facilities, which were first established in the 1970s. Ibrahim said Intel’s head of foundry, Naga Chandrasekaran, has “outlined a plan to launch the first phase” of the expansion, which will include advanced packaging.
“I welcome Intel’s decision to begin operations for the complex later this year,” a translated version of Ibrahim’s post reads. Intel spokesperson, John Hipsher, confirmed that it is building additional chip assembly and test capacity in Penang “amid the growing global demand for Intel Foundry packaging solutions”.
package shop
According to Chandrasekaran, who took over Intel’s foundry operations in 2025 and spoke exclusively with WIRED during the reporting of this story, the term “advanced packaging” didn’t exist a decade ago.
Chips have always required some form of integration of transistors and capacitors, which control and store energy. For a long time the semiconductor industry was focused on miniaturization, or, reducing the size of components on chips. As the world began to demand more from its computers in the 2010s, chips began to become even more dense with processing units, high-bandwidth memory, and all the necessary connective parts. Eventually, chip manufacturers began adopting a system-in-package or package-on-package approach, in which multiple components were placed on top of each other to squeeze more power and memory from the same surface space. 2D stacking gave way to 3D stacking.
TSMC, the world’s leading semiconductor manufacturer, began offering customers packaging technologies such as CoWoS (chip on wafer on substrate) and, later, SoIC (system on an integrated chip). Essentially, the pitch was that TSMC would handle not only the front end of chip-making – the wafer part – but also the back end, where all the chip technology would be packaged together.
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